53236-580-00 c fas216/216u/236/236u 1 features n host application and 16-bit peripheral application support n compliance with ansi scsi standard x3.131-1994 n compliance with ansi scsi con?gured automatically (scam) protocol levels 1 and 2 n compliance with ansi x3t10/855d scsi-3 parallel interface (spi) standard n compliance with ansi x3t10/1071d fast-20 standard n asynchronous data transfers up to 7 mbytes/sec n synchronous data transfers up to 5 mbytes/sec (normal scsi), 10 mbytes/sec (fast scsi), and 20 mbytes/sec (ultra scsi) r programmable synchronous transfer period r programmable synchronous transfer offsets up to 15 bytes n 24-bit transfer counter n initiator and target modes n differential driver protection (diffsens) n direct memory access (dma) burst transfer rate up to 20 mbytes/sec n pipelined command structure n 16-byte data fifo between dma and scsi channels n parity pass-through on fifo data n part-unique id code n on-chip, single-ended scsi transceivers (48-ma drivers) n clock rates up to 40 mhz figure 1. fas2x6 block diagram sequencers fifo scsi control scsi data clock conversion db bus sync offset/ sync assert/ sync deassert sync period sequence step status interrupt command transfer counter pad bus sel/resel bus id sel/resel timeout transfer count register bus (in) register bus (out) configuration test (scam) note: scam applies to the FAS216U and fas236u only. qlogic corporation fas216/216u/236/236u fast architecture scsi processor data sheet
2 fas216/216u/236/236u 53236-580-00 c qlogic corporation note: throughout this data sheet, the term fas2x6 refers to the fas216, FAS216U, fas236, and fas236u unless otherwise noted. product description the fas2x6 chips are part of the qlogic scsi processor family with features designed to facilitate scsi-2 support (fas216 and fas236) and scsi-3 support (FAS216U and fas236u). the fas216 and fas236 can transfer synchronous data at 10 mbytes/sec. the FAS216U and fas236u can transfer data at 20 mbytes/sec with scam support. the normal 5-mbytes/sec transfer rate and the fast 10-mbytes/sec transfer rate (FAS216U and fas236u) are supported on-chip by setting the fastscsi bit (con?guration 3 register bit 4). asynchronous transfers up to 7 mbytes/sec are also supported. the FAS216U and fas236u chips are ?rmware and pin compatible with the fas216 and fas236 chips, respectively. figure 1 shows the fas2x6 block diagram. the fas2x6 replaces existing scsi interface circuitry, which typically consists of discrete devices, an external driver, and a low-performance scsi interface chip. the fas2x6 contains a fast dma interface; a 16-byte fifo; and fast asynchronous and synchronous data interfaces to the scsi bus, including drivers in single-ended mode. differential mode requires external drivers. the fas216 and FAS216U support single-ended mode; the fas236 and fas236u support single-ended and differential modes. since the fas2x6 operates in both initiator and target modes, it can be used in both host and peripheral applications. the chip performs such functions as bus arbitration, selection of a target, and reselection of an initiator. the fas2x6 also handles message, command, status, and data transfers between the scsi bus and its internal fifo or between the scsi bus and buffer memory. the chip maximizes protocol ef?ciency by utilizing a fifo command pipeline and combination commands to minimize host intervention. differential driver protection (fas236/236u only) the fas236/236u pins 5 (diffsens) and 7 (ediffs) support the scsi diffsens differential driver protection function. the diffsens function is enabled in differential mode when pins 5 and 7 are pulled up by an external device. the fas236/236u is con?gured for differential mode operations when pin 87 (diffm) is low. if a single-ended device or terminator is connected while the chip is con?gured for differential operations, diffsens becomes grounded, disabling the differential drivers. the gross error bit (status register bit 6) is set and a disconnect interrupt is generated. the gross error bit and the disconnect interrupt are asserted as long as the diffsens condition exists. the diffsens function has no effect in single-ended mode. scam implementation the FAS216U and fas236u support levels 1 and 2 of the scam protocol. scam protocol requires direct access and control over the scsi data bus and several of the scsi phase and control signals. the majority of the scam protocol can be implemented in ?rmware at microprocessor speeds. the following scam features are supported in the chip hardware: n arbitration without an id n slow response to selection with an uncon?rmed id n detection of and response to scam selection system organization the fas2x6 controller systems support three main buses: the 8- or 16-bit data bus (db), the 8-bit microprocessor address and data bus (pad), and the 8-bit scsi bus. the db provides a path for dma transfers through the fifo. the pad bus provides access to all internal registers. the fas2x6 supports parity pass-through from the scsi bus through the fifo to the db. this versatile split-bus architecture separates the two high-traf?c information ?ows, the scsi bus and db bus, to provide maximum ef?ciency and throughput. single- or split-bus con?gurations with 8- or 16-bit dma are pin selectable. table 1 shows chip operating conditions. interfaces the fas2x6 acts as an interface between the microprocessor and the scsi bus in target or initiator mode. the other interfaces are described below: n microprocessor interface. the db or pad bus is the microprocessor interface to the fas2x6. both buses allow the microprocessor 8-bit read and write access to all chip registers, including the fifo. the pad bus allows microprocessor interface to the chip registers independent of dma activity on the db. n dma interface. the fas2x6 logic transfers data to and from a buffer over the db con?gured as 8 or 16 bits. (each byte on the bus has its own parity.) if byte control mode (con?guration 2 register bit 5) is set, an external dma controller can dictate how the bytes are placed on the bus. packaging the pin diagrams for the fas216/216u and fas236/236u are shown in ?gures 2 and 3. pins that support the fas216/216u and fas236/236u operations are shown in ?gures 4 and 5. dimensions for the fas216/216u 84-pin plastic leaderless chip carrier (plcc) and the fas236/236u 100-pin plastic quad ?at pack (pqfp) are shown in ?gures 6 and 7.
53236-580-00 c fas216/216u/236/236u 3 qlogic corporation figure 2. fas216/216u 84-pin plcc pin diagram 70 69 68 66 fas216/216u 84-pin plcc 14 13 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 58 59 60 61 62 63 64 65 db4 67 71 72 73 74 db3 db5 db6 db7 dbp0 vss db8 db10 db11 db12 db13 db14 db15 29 30 31 32 54 55 56 57 db9 dbp1 vss vss db0 db1 db2 sdi0 sdi1 sdi2 sdi3 sdi4 sdi5 sdi6 sdi7 sdip vdd vss sdo0 sdo1 sdo2 sdo3 vss sdo5 sdo6 sdo7 sdop vss selo bsy o reqo a ck o vss msg cd io a tn rst o vss seli bsyi reqi a cki rsti mode1 mode0 int reset dbwr d a ck dreq pad7 pad6 pad5 pad4 vss pad3 pad2 pad1 pad0 vdd ck a3, ale a2, dbrd a1, bhe a0, sa0 cs rd wr sdo4 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
4 fas216/216u/236/236u 53236-580-00 c qlogic corporation figure 3. fas236/236u pin diagram fas236/236u 100-pin pqfp d a ck dbwr nc igs diffsens tgs ediffs db0 db1 db2 db3 db4 db5 db6 db7 dbp0 vss vss db9 db10 db8 db11 db12 db13 db14 db15 dbp1 nc sdi0 sdi1 sdo7 sdop nc vss vss selo bsy o reqo a ck o vss vss msg cd io a tn rst o vss vss seli bsyi reqi a cki rsti mode1 mode0 int reset nc wr rd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 3 4 5 6 7 8 9 26 27 28 29 30 1 sdo6 sdi2 sdi3 sdi4 sdi5 sdi6 sdi7 sdip vdd nc vss vss sdo0 sdo1 sdo2 sdo3 vss vss sdo4 sdo5 dreq pad7 pad6 pad5 pad4 vss vss pad3 pad2 pad1 pad0 nc vdd diffm ck a3, ale a2, dbrd a1, bhe a0, sa0 cs
53236-580-00 c fas216/216u/236/236u 5 qlogic corporation misc figure 4. fas216/216u functional signal grouping a1, bhe microprocessor interface vdd vss power and ground ck clock rst o rsti bsy o scsi interface fas216/216u cs a3, ale d a ck dma and microprocessor interface a0, sa0 a2, dbrd pad7-0 int mode1-0 dbwr dreq dbp1-0 sdip, sdi7-0 sdop, sdo7-0 db15-0 rd 57 20, 19-12 58 32, 31-28, 26-23 59 43 60 49 56 35 52 71-68, 66-63 55 73 72 74 11, 1 10-3, 84-77 61 21, 62 see note 50, 51 note: vss = 2, 22, 27, 33, 38, 44, 67, 75, 76 wr 54 reset reset 53 bsyi 46 selo 34 seli 45 reqo 36 reqi 47 a ck o 37 a cki 48 a tn 42 msg 39 cd 40 io 41
6 fas216/216u/236/236u 53236-580-00 c qlogic corporation figure 5. fas236/236u functional signal grouping a1, bhe microprocessor interface vdd vss power and ground ck clock rst o rsti bsy o scsi interface fas236/236u cs a3, ale d a ck dma and microprocessor interface a0, sa0 a2, dbrd pad7-0 int mode1-0 misc dbwr dreq dbp1-0 sdip, sdi7-0 sdop, sdo7-0 db15-0 rd 82 37, 36-29 83 52, 51-48, 45-42 84 66 85 73 81 57 76 99-96, 93-90 80 1 100 2 27, 16 26-19, 15-8 86 38, 88 see note 74, 75 note: vss = 17, 18, 40, 41, 46, 47, 54, 55, 60, 61, 67, 68, 94, 95 wr 79 reset reset 77 bsyi 70 selo 56 seli 69 reqo 58 reqi 71 a ck o 59 a cki 72 a tn 65 msg 62 cd 63 io 64 diffm 87 igs external transceiver control 4 tgs 6 no connect diffsens 5 ediffs 7 3, 28, 39, 53, 78,89
53236-580-00 c fas216/216u/236/236u 7 qlogic corporation figure 6. fas216/216u 84-pin plcc mechanical drawings 0.45 0.576 1.153 sq (nom) pin 1 indicator 0.05 (nom) 0.576 1.19 sq (nom) 0.045 x 45 chfr 0.072 (nom) 0.093 (nom) 0.028 (nom) 0.018 (nom) 0.045 x 45 chfr 0.15 (nom) 0.175 (nom) 1.12 sq (nom) 0.025 (nom) 0.107 (nom) note: all dimensions are in inches. all dimensions are nominal unless specified otherwise. 0.010 x 45 chfr (3) figure 7. fas236/236u 100-pin pqfp mechanical drawings 20.00 23.9 0.25 14.00 17.9 0.25 index mark a 0.8 + 0.15 0.22 min detail a 0.65 bsc 4 typical pin 1 pin 31 pin 50 pin 30 pin 100 pin 51 pin 80 pin 81 0.13 min 3.4 max note: all dimensions are in millimeters. all dimensions are nominal unless specified otherwise. 1.95 ref 0.13 min 0.23 max 0.38 max
8 fas216/216u/236/236u 53236-580-00 c qlogic corporation electrical characteristics table 1. operating conditions symbol description minimum maximum unit vdd supply voltage 4.75 5.25 v idd a supply current (static idd) 4 ma idd b supply current (dynamic idd) 40-60 ma ta ambient temperature 0 70 o c t able notes conditions not within operating conditions but within the absolute maximum stress ratings may cause the chip to malfunction. a static idd is measured with no clocks running and all inputs forced to vdd, all outputs unloaded, and all bidirectional pins con?gured as inputs. b dynamic idd is dependent on the application. ?october 4, 1996 qlogic corporation, 3545 harbor blvd., costa mesa, ca 92626, (800) on-chip-1 or (714) 438-2200 speci?cations are subject to change without notice. qlogic is a trademark of qlogic corporation.
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